
Senior Design Engineer
2 weeks ago
The position involves working with a seasoned physical design team to deliver the physical design of tiles and FullChip. The ideal candidate has significant industry experience, excellent analytical and problem-solving skills, and good communication and presentation skills.
Key Responsibilities:
- RTL to GDS2 flow
- Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
- Different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
- Identify and implement opportunities for improving PPA
Requirements:
- 12+ years of professional experience in physical design, preferably with high performance designs.
- Automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
- Clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
- Floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
- Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality.
- STA, full chip timing
- Versatility with scripts to automate design flow.
- Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams.
- FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm.
- Excellent physical design and timing background.
- Good understanding of computer organization/architecture is preferred.
- Strong analytical/problem solving skills and pronounced attention to details.
Qualifications:
- Bachelors or Masters in Electronics/Electrical Engineering.
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