Senior Verification Engineer, Digital Systems
24 hours ago
Job Summary:
We are seeking a highly skilled Senior Verification Engineer to join our team. In this role, you will be responsible for planning and executing the verification of next-generation infrastructure IPs, interconnects, and memory subsystems.
Key Responsibilities:
- Develop constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM).
- Design and enhance cross-language tools and scalable verification methodologies.
- Collaborate with design engineers to debug tests and ensure verification progress toward tape-out.
Requirements:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience in verifying digital systems, RTL verification using SystemVerilog or C/C++, and scripting languages.
- Familiarity with performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation.
- Proficient in creating verification components and environments using standard verification methodologies like UVM and SystemVerilog.
About the Role:
This is an excellent opportunity to work on cutting-edge technology and contribute to the development of innovative solutions. If you are a motivated and detail-oriented individual with a passion for digital systems verification, we encourage you to apply.
What We Offer:
- A dynamic and supportive work environment.
- Ongoing training and professional development opportunities.
- A competitive salary and benefits package.
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