
ASIC Design For Testability Professional
1 day ago
We are seeking an experienced ASIC Design for Testability Engineer to join our team. The ideal candidate will have a strong background in design and experience with testability concepts, pattern simulation, silicon debug, and yield enhancement.
Key Responsibilities:- Interface with design teams to ensure testability design rules and coverages are met.
- Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models through the use of on-chip test compression techniques.
- MBIST verification (including repair), test pattern generation through Mentor tool.
- ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
- Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
- Responsible for supporting post-silicon debug effort, issue resolution.
- Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.
- Developing, enhancing and maintaining scripts as necessary.
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering.
- Minimum of 4 to 12 years' experience in ASIC/DFT - simulation and Silicon validation.
- Should have worked in at least one Full chip DFT.
- Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement.
- In-depth knowledge and hands-on experience in ATPG - coverage analysis.
- In-depth knowledge of Memory verification, repair and failure root-cause analysis.
- Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim.
- Expertise in scripting languages such as Perl, shell, etc. is an added advantage.
- Ability to work in an international team, dynamic environment with good communication skills.
- Ability to learn and adapt to new tools, methodologies.
- Ability to do multi-tasking & work on several high-priority designs in parallel.
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