Physical Chip Architect

5 days ago

Thāne, Maharashtra, India beBeeDesigner Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Senior ASIC Physical Designer

In this role, you will be responsible for leading all aspects of physical design for full-chip and block-level projects. Your key responsibilities include:

Main Responsibilities:
  • Floorplanning: Create efficient floorplans to optimize performance and power consumption.
  • Placement: Place components on the chip to minimize area and reduce timing closure issues.
  • Budgeting: Establish realistic timing budgets and constraints.
  • Clock Tree Planning & Analysis: Design and optimize clock networks to meet performance and power requirements.
  • Scan Re-ordering: Implement scan chains to ensure testability and debuggability.
  • Clock Tree Synthesis: Generate clock networks from timing specifications.
  • Placement Optimizations: Apply optimization techniques to improve placement quality.
  • Routing: Route signals between components to meet timing and noise requirements.
  • Timing and SI Analysis/Closure: Analyze and close timing and signal integrity (SI) issues.
  • ECO Tasks (both timing and functional): Perform engineering change orders (ECOs) to fix timing and functional issues.
  • EM/IR, DRC, LVS, ERC Analysis & Fixes: Identify and fix electromagnetic interference (EMI), inductive ringing (IR), design rule check (DRC), layout-versus-schematic (LVS), and electrical rule check (ERC) issues.
  • Low Power Solution Development & Implementation: Develop and implement low-power design techniques to reduce power consumption.

You will work closely with the methodology team to solve implementation challenges and provide inputs to improve the physical design flow. Additionally, you will have experience in design automation and proficiently use EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, and Calibre.

Requirements:
  • 4+ years of experience in ASIC physical design.
  • Experience with block implementation, extraction, timing, and or full-chip designs.
  • Strong communication skills.
  • Strong hands-on TCL/Perl development skills.
  • Must have prior experience with Synopsys/Cadence/Mentor place and route tools.
  • Must have completed design in 16nm and or 7nm.

This role requires good interpersonal skills, problem-solving ability, and strong communication and presentation skills.

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