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2 days ago
We are seeking a seasoned Physical Design Engineer to drive the development of complex ASICs. This role involves providing technical guidance and expertise in physical design methodologies.
Responsibilities:
- Provide technical leadership and mentorship to junior engineers.
- Collaborate with cross-functional teams to resolve technical issues.
- Design power-efficient solutions utilizing advanced techniques such as voltage islands, power gating, and substrate biasing.
- Ensure timing closure on DDR2/DDR3/PCIE interfaces.
- Communicate effectively with stakeholders to prioritize work based on project needs.
Requirements:
- 4-12 years of experience in ASIC physical design.
- Expertise in Cadence or Synopsys or Magma physical design tools.
- Strong knowledge of scripting languages such as PERL and TCL.
- Extensive experience in static timing analysis and signal integrity closure.
- Good written and oral communication skills.
Key Skills:
- Floor planning, placement, partitioning, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, and ECO tasks.
- Low power design techniques such as Voltage Islands, Power Gating, and substrate-bias.
- Timing closure on DDR2/DDR3/PCIE interfaces.
- Static timing analysis and signal integrity closure.
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