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Optimizing Custom Memory Solutions
3 weeks ago
As a Memory Layout Engineer, you will play a pivotal role in designing and optimizing memory layouts for custom memories such as SRAM and Register Files.
Key Responsibilities- Collaborate with circuit designers to understand schematics and translate them into optimized layouts
- Work closely with the design team to ensure seamless integration of memory layouts
- Develop a strong understanding of floor-planning, placement, matching, routing, parasitics, and layout constraints
- Implement physical verification checks, including DRC, LVS, ERC, EM, and IR reliability checks
- Stay up-to-date with the latest advancements in process nodes, particularly those below 5nm
- Minimum 5+ years of experience in memory layout design
- Strong understanding of custom-based memories or compiler-based memories
- Experience with scripting languages such as SKILL, Python, or TCL
- Familiarity with high-performance and low-power memory layout optimization techniques
- Advanced knowledge of process nodes, particularly those below 5nm
- Proficiency in programming languages and design automation tools
This is a challenging opportunity for someone who thrives on innovation and problem-solving. If you have a passion for designing and optimizing complex memory layouts, we encourage you to apply.
