**High Performance Logic Design Engineer

2 weeks ago

Bengaluru, Karnataka, India Mulya Technologies Full time
{"Role and Responsibilities":{"html":"

As a Senior Logic Design Engineer at Mulya Technologies, you will lead the architecture, design, and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core, and multi-socket SMP (symmetric multi-processor) system.

You will develop the features, present the proposed architecture in high-level design discussions to hardware and software teams, and collaborate with the verification, DFT, physical design, firmware, and software teams to develop the feature.

You will be responsible for signoff of pre-silicon design that meets all functional, area, and timing goals, participate in silicon bring-up and validation of the hardware, and lead a team of engineers, guiding and mentoring team members, representing as Logic Design Lead in global forums.

","text":"As a Senior Logic Design Engineer at Mulya Technologies, you will lead the architecture, design, and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core, and multi-socket SMP system. You will develop the features, present the proposed architecture in high-level design discussions to hardware and software teams, and collaborate with the verification, DFT, physical design, firmware, and software teams to develop the feature. You will be responsible for signoff of pre-silicon design that meets all functional, area, and timing goals, participate in silicon bring-up and validation of the hardware, and lead a team of engineers, guiding and mentoring team members, representing as Logic Design Lead in global forums."},"Technical and Professional Expertise":{"html":"

We are seeking a highly experienced Senior Logic Design Engineer with a strong background in SMP coherency, processor interconnect design, and high-speed logic design.

Key qualifications include:

  • 8 to 15 years of relevant experience
  • At least 1 generation of processor interconnect design delivery leadership (e.g., UPI, AXI, AMBA, NoC)
  • Expertise in SMP coherency
  • Experience in different on-chip interconnect topologies (e.g., mesh, crossbar)
  • Understanding of various snoop and data network protocols
  • Understanding of latency and bandwidth requirements and effective means of implementation
  • Working knowledge of queuing theory, numa/nuca architecture
  • Proficient in HDLs - VHDL / Verilog
  • Experience in high-speed and power-efficient logic design
  • Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage
  • Good understanding of physical design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design
  • Experience in leading uarch, RTL design teams for feature enhancements.
","text":"We are seeking a highly experienced Senior Logic Design Engineer with a strong background in SMP coherency, processor interconnect design, and high-speed logic design. Key qualifications include: 8 to 15 years of relevant experience, at least 1 generation of processor interconnect design delivery leadership (e.g., UPI, AXI, AMBA, NoC), expertise in SMP coherency, experience in different on-chip interconnect topologies (e.g., mesh, crossbar), understanding of various snoop and data network protocols, understanding of latency and bandwidth requirements and effective means of implementation, working knowledge of queuing theory, numa/nuca architecture, proficient in HDLs - VHDL / Verilog, experience in high-speed and power-efficient logic design, experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage, good understanding of physical design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design, experience in leading uarch, RTL design teams for feature enhancements."}},"Requirements":{"html":"

Masters in VLSI with demonstrated experience in the microarchitecture and design of state-of-the-art processor features to enhance high-performance secure system performance.

","text":"Masters in VLSI with demonstrated experience in the microarchitecture and design of state-of-the-art processor features to enhance high-performance secure system performance."},"Preferred Technical and Professional Experience":{"html":"

None

","text":"None"},"Preferred Education":{"html":"

Master's Degree

","text":"Master's Degree"},"Contact":{"html":"

","text":""},"Language":{"html":"

","text":"en"}

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