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Senior Logic Design Engineer for High-Performance Systems
2 months ago
Job Description
We are seeking a highly skilled Logic Design Engineer to join our team at Mulya Technologies. As a member of our Systems division, you will be responsible for designing and developing high-performance, low-latency on-chip interconnects (NoC) and chip-to-chip interconnects.
Key Responsibilities
- Design and architect different interconnect topologies to meet bandwidth, latency, and RAS requirements.
- Develop features, present proposed architectures in high-level design discussions, and collaborate with verification, DFT, physical design, FW, and SW teams to develop features.
- Sign off on pre-silicon designs that meet all functional, area, and timing goals.
- Participate in silicon bring-up and validation of hardware.
Requirements
- 6-15+ years of relevant experience.
- At least 1 generation of processor interconnect design delivery leadership.
- Expertise in SMP coherency, on-chip interconnect topologies, snoop and data network protocols, latency & bandwidth requirements, and queuing theory.
- Proficient in HDLs - VHDL/Verilog and experience in high-speed and power-efficient logic design.
- Experience in working with verification, validation, physical design teams for design closure.
- Master's Degree in VLSI with demonstrated experience in micro-architecture and design of state-of-the-art processor features.
Contact
Uday at Mulya Technologies.
