
High Performance AI Accelerator Designer
1 day ago
We are seeking a seasoned Senior AI Accelerator Architect to lead the development of high-performance accelerators from scratch.
This key role involves collaborating with cross-functional teams, including architects, software engineers, and systems engineers, to define and implement next-generation AI architectures.
Key responsibilities include:
- Designing and implementing high-performance TPUs/MPUs and other related AI blocks using RTL.
- Owning IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure.
- Optimizing designs for power, performance, and area (PPA).
- Interfacing with physical design and DFT engineers for seamless integration.
- Driving design reviews, writing design documentation, and supporting post-silicon bring-up/debug.
The ideal candidate will possess a clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts, as well as strong grasp of digital design fundamentals, computer architecture, virtual memory, and high-speed data-path design.
Proficiency in Verilog/SystemVerilog and simulation tools is required, along with experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis.
A B.S./M.S./Ph.D. degree in ECE/CS from top engineering colleges with 5-15 years of related experience is essential. Previous experience in high-performance processor design or AI accelerator design is a plus.
Mulya Technologies offers competitive compensation packages and opportunities for growth and professional development. If you are passionate about innovation and excited about creating world-class products, please submit your application.
Bachelors, Masters, Phd. degree in electronics and communication engineering/computer science from top engineering college
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