Senior VLSI Design Engineer
5 days ago
We are seeking a highly skilled Senior VLSI Design Engineer with expertise in Static Timing Analysis to join our team at LeadSoc Technologies Pvt Ltd.
About the Role:
- Lead and execute static timing analysis for complex digital designs
- Develop and implement constraint handling strategies for functional and test-related issues
- Collaborate with cross-functional teams for ECO generation and implementation at top-level
- Drive automation efforts using Perl, Tcl, Awk, and Python for synthesis and other tasks
Requirements:
- 5+ years of experience in STA, preferably with exposure to lower nodes (3nm, 5nm)
- Proven track record of delivering projects on time with high quality
- Strong communication and collaboration skills
Benefits:
- Average salary ₹1,200,000 - ₹1,500,000 per annum based on experience
- Opportunity to work with a cutting-edge technology company
- Competitive benefits package including medical insurance, retirement plan, etc.
Location: Bangalore
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