Senior Interconnect Architect

2 days ago


Dombivli, Maharashtra, India beBeeInterconnect Full time ₹ 2,00,00,000 - ₹ 3,00,00,000
Job Opportunity

We are seeking a seasoned professional to lead the development of cutting-edge interconnect solutions. As a CPU Architecture and Logic Design Lead, you will be responsible for designing and architecting high-bandwidth, low-latency on-chip interconnects (NoCs) and chip-to-chip interconnects that integrate seamlessly into high-performance systems.

Your primary focus will be on:

  • Designing various interconnect topologies that meet bandwidth, latency, and RAS requirements
  • Developing features and presenting proposed architectures in high-level design discussions
  • Collaborating with verification, DFT, physical design, FW, and SW teams to develop and implement features
  • Ensuring pre-silicon designs meet functional, area, and timing goals
  • Participating in silicon bring-up and validation of hardware
Requirements

To succeed in this role, you must possess:

  • At least 1 generation of processor interconnect design delivery leadership experience (e.g., UPI, AXI, AMBA, NoC)
  • Expertise in SMP coherency and understanding of various snoop and data network protocols
  • Experience with different on-chip interconnect topologies (e.g., mesh, crossbar)
  • Strong understanding of latency and bandwidth requirements, as well as effective implementation methods
  • Working knowledge of queuing theory and familiarity with Numa/Nuca architecture
  • Proficiency in HDLs (VHDL/Verilog) and experience with high-speed and power-efficient logic design
  • Ability to collaborate with verification, validation, and physical design teams for design closure, including test plan reviews and verification coverage
  • Experience leading uarch and RTL design teams for feature enhancements
Preferred Qualifications

Prior experience with High-Performance Computing (HPC) environments and expertise in Physical Design would be highly advantageous.



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