Memory Layout Developer

Experience Level 3 to 8 Years ( Mid-Level Role)Responsibilities:As Memory Layout Engineer, we will work on developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding PPA.Required Skills and Experience :We Prefer graduate or postgraduate from a University or Engineering School, in Electronic...

Job OverviewThis role requires a deep understanding of memory layout design principles and the ability to collaborate with circuit designers. As a specialist in custom-based memories or compiler-based memories, you will utilize high-performance and/or low-power memory layout optimization techniques to create efficient designs.Responsibilities:Design and...

Design and Optimize Memory Layouts for Efficient System PerformanceWe are seeking a highly skilled Memory Layout Engineer to join our team. As a key member of our organization, you will be responsible for designing and optimizing memory layouts to achieve efficient system performance.Key Responsibilities:Design efficient memory layouts with good debugging...

Memory Designer for Advanced NodesThis role involves creating highly optimized and manufacturable memory designs for leading-edge nodes.Prior experience with full-custom memory design and architectures is essential.Proficiency in working with SRAM leafcells from scratch to top-level integration is required.Familiarity with advanced process nodes such as 7nm,...

Job Title: Senior Design Engineer\The primary responsibility of this position is to develop memory compilers and Fast Cache instances for our next generation Cores, achieving outstanding PPA. This requires a strong understanding of computer architecture and concepts, as well as experience in design verification, SRAM architecture, Critical Path Modelling,...

About UsWe're on a mission to revolutionize computing with our cutting-edge AI-powered predictive memory technology. Our innovative solution makes Flash storage appear as DRAM-speed memory, empowering customers to run applications within a far smaller DRAM footprint. This yields up to 40% lower operational expenditure in the cloud and up to 50% lower capital...

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