Senior ASIC Design Engineer

6 days ago


Hubli, Karnataka, India beBeeTiming Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Job Title:

Synthesis and Static Timing Analysis

Summary:

Lead the synthesis, static timing and DFT efforts for an advanced mixed-signal chip in a high-profile startup.

Key Responsibilities:
  • Own full chip and block level timing closure throughout the entire project cycle (RTL, synthesis, and physical implementation).
  • Develop and maintain methodology and flows related to timing verification and closure.
  • Generate block and full chip timing constraints.
  • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
Requirements:
  • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
  • Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl).
Benefits:
  • Opportunity to work on cutting-edge mixed-signal chip projects.
  • Collaborative and dynamic work environment.
  • Chance to develop skills in state-of-the-art technologies and methodologies.
About Us:

Our company is a leading provider of semiconductor solutions. We are committed to delivering innovative products and services that meet the evolving needs of our customers.



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