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2 days ago
We're seeking a seasoned professional to assume a key role in our digital design team. As a Design Engineering Leader, you will be responsible for delivering high-quality designs that meet the needs of our customers.
Key Responsibilities:- Block level Netlist to GDS delivery
- Subsystem level floorplan, PnR and timing closure
- FCFP/FCI/FCT activities - Full Chip Floor planning, Full chip Integration, Full Chip timing
- Leading/Guiding a team of 2-3 Engineers
- 5+ years of experience in PnR and STA
- Hands-on experience in RTL/Netlist to GDS delivery of blocks
- Good understanding of DFT stitching and clock tree strategies
- Strong at density and congestion issues resolution
- Complex blocks floorplan, PnR and STA such as DDRIP. PCIE IP
- Capable of doing PV and IREM fixes along with the timing
- Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies
- TCL and PERL scripting knowledge and experience in writing the scripts
- Good exposure to Cadence EDA tool set needed for PD
- A challenging opportunity to grow professionally and personally
- A dynamic work environment that encourages innovation and teamwork
- The chance to make a real impact on the development of cutting-edge technology
- We're a company that values creativity, collaboration, and continuous learning
- We're passionate about solving complex problems and pushing the boundaries of what's possible
- We offer a competitive compensation package and excellent benefits
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