Expert Block-Level Physical Designer

5 days ago

Hyderabad, Telangana, India beBeeDesign Full time ₹ 18,00,000 - ₹ 25,00,000
Lead PNR Activities

As a Senior Engineer in Product Design Engineering, you will lead block-level PNR activities from floorplanning through final routing. Your primary responsibility will be to ensure robust physical implementation aligned with timing, power, and area goals.


  • Drive power grid design and EM/IR-aware routing strategies to guarantee block-level power integrity and reliability.
  • Collaborate closely with timing closure engineers to resolve physical design bottlenecks impacting timing and signal integrity.
  • Automate PNR flows and develop scripts to improve productivity and design quality.
  • Mentor and guide junior physical design engineers, fostering technical growth and best practices.
  • Coordinate with cross-functional teams including RTL design, STA, verification, and backend.


8+ years of experience in physical design with a strong focus on block-level Place and Route (PNR) for complex SoC/IP subsystems, preferably at advanced technology nodes (16nm, 7nm, 5nm, or below).


  • Proven expertise in block-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (DRC/LVS).
  • Hands-on experience with industry-standard PNR tools such as Cadence Innovus, Synopsys ICC2, and Mentor Calibre.
  • Strong understanding of power grid design, EM/IR analysis, signal integrity (SI), and reliability checks at the block level.
  • Experience in managing timing closure in coordination with STA teams, resolving congestion, and optimizing for power, performance, and area (PPA).
  • Proficiency in scripting languages (Tcl, Python, Perl) for flow automation and custom tool development.
  • Demonstrated ability to lead block PNR efforts, coordinate with RTL designers, physical design teams, and verification groups to meet aggressive tapeout schedules.
  • Familiarity with low-power design techniques and power-aware physical implementation.

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