Expert Block-Level Design Lead

5 days ago

Hyderabad, Telangana, India beBeePhysicalDesign Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Senior Physical Design Engineer

We are seeking an exceptional individual to lead our block-level PNR activities from floorplanning through final routing, ensuring a robust physical implementation that aligns with timing, power, and area goals.

The ideal candidate will have 8+ years of experience in physical design with a strong focus on block-level Place and Route (PNR) for complex SoC/IP subsystems, preferably at advanced technology nodes (16nm, 7nm, 5nm, or below).

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  • Driving power grid design and EM/IR-aware routing strategies to ensure block-level power integrity and reliability.">
  • Collaborating closely with timing closure engineers to resolve physical design bottlenecks impacting timing and signal integrity.">
  • Managing and optimizing physical verification flows including DRC, LVS, antenna checks, and physical signoff.">

The candidate should have hands-on experience with industry-standard PNR tools such as Cadence Innovus, Synopsys ICC2, and Mentor Calibre, and proficiency in scripting languages (Tcl, Python, Perl) for flow automation and custom tool development.

A strong understanding of power grid design, EM/IR analysis, signal integrity (SI), and reliability checks at the block level is required, along with experience in managing timing closure in coordination with STA teams, resolving congestion, and optimizing for power, performance, and area (PPA).

Familiarity with low-power design techniques and power-aware physical implementation is also desirable.

The selected candidate will mentor and guide junior physical design engineers, fostering technical growth and best practices, and coordinate with cross-functional teams including RTL design, STA, verification, and backend integration to ensure seamless block-to-chip integration.

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