Advanced SoC Architectural Designer
5 days ago
Our team is seeking a skilled Digital Fault Tolerance (DFT) Engineer to develop and implement DFT architecture with a focus on Built-In Self-Test (BIST) for advanced System-on-Chips (SoCs).
- Design and integrate BIST Intellectual Properties (IPs), generate test insertion and verification infrastructure.
- Work on DFT planning, insertion, simulation, and pattern generation.
- Perform Automatic Test Pattern Generation (ATPG) and BIST pattern generation, and debug failures from silicon bring-up.
- Collaborate with Register Transfer Level (RTL), Physical Design, and Verification teams throughout the design cycle.
- Support silicon bring-up and yield improvement activities post-silicon.
- Ensure high coverage and test quality in scan and BIST.
Required Skills and Qualifications:
- Bachelor's or Master's degree in Electronics or related field.
- Minimum 7+ years of hands-on experience in DFT with a strong focus on ATPG, SCAN and BIST
- Proficient in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent.
- Solid understanding of scan insertion, ATPG, boundary scan, and JTAG.
- Experience with memory test algorithms, repair analysis, and pattern generation.
- Familiarity with scripting languages (TCL, Perl, Python) for automation.
- Strong analytical and problem-solving skills with the ability to work independently
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