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Senior DFT Engineer
2 weeks ago
Job Title: DFT Architect
Location: Kollam, India
Employment Type: Full-time
Industry: Semiconductors / ASIC / SoC Design
We are seeking an experienced technical leader to drive the development and implementation of advanced test methodologies for complex SoC/ASIC designs. As a lead architect, you will be responsible for designing and implementing robust and efficient test architectures that ensure world-class testability and manufacturability of silicon products.
Key Responsibilities:
- Develop and implement comprehensive DFT strategies for multiple ASIC/SoC projects.
- Lead the implementation and verification of DFT features such as scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, and IJTAG.
- Manage the end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
- Collaborate with cross-functional teams including RTL, STA, PD, and test engineering teams for seamless integration.
- Perform pattern generation, fault simulation, and debug test coverage gaps.
- Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
- Support silicon bring-up, test vector validation on ATE, and yield optimization.
- Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
- Develop and maintain DFT automation scripts and infrastructure.
Required Skills and Qualifications:
- Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
- 7+ years of experience in DFT for complex ASIC or SoC designs.
- Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
- Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.
- Strong knowledge of RTL design, STA, and synthesis flows.
- Proficient in scripting languages for flow automation.
- Deep understanding of silicon test challenges and test coverage improvement.
- Strong leadership, team collaboration, and communication skills.