
Highly Skilled Designer Required
2 days ago
We are seeking a skilled Senior Physical Design Engineer to join our team. This is an exciting opportunity for experienced professionals to leverage their expertise in ASIC physical design, leveraging cutting-edge tools and techniques to deliver innovative solutions.
About the Role:
- The successful candidate will provide technical guidance and mentoring to junior engineers, driving knowledge sharing and growth within the team.
- Interface with cross-functional teams, including front-end ASIC teams, to resolve complex issues and ensure seamless project execution.
- Leverage strong analytical skills to develop low power designs, utilizing techniques such as Voltage Islands, Power Gating, and substrate-bias.
- Achieve timing closure on DDR2/DDR3/PCIE interfaces, ensuring robust and efficient system performance.
- Collaborate effectively with stakeholders to communicate technical concepts and drive project success.
- Maintain a deep understanding of ASIC physical design principles, including floor planning, placement, routing, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Possess extensive experience with Cadence or Synopsys or Magma physical design tools, scripting languages like PERL and TCL.
- Demonstrate strong Physical Verification skills, performing Static Timing Analysis in Primetime or Primetime-SI.
Requirements:
- 4-12 years of experience in physical design engineering, with a proven track record of delivering high-quality results.
- Excellent written and oral communication skills, with the ability to clearly document plans and collaborate effectively.
- Capacity to interface with different teams, prioritize work based on project needs, and drive project success.
Essential Skills:
- Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
- Experience with 65nm or lower node designs, leveraging advanced low power techniques to deliver optimized solutions.
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