Senior Design Engineer

6 days ago

Bareilly, Uttar Pradesh, India beBeeEngineer Full time ₹ 20,00,000 - ₹ 25,00,000
Job Description

As a seasoned engineer, you will lead Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems, focusing on robust timing closure and physical implementation optimization.

Develop methodologies tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems. Drive automation and validation of timing and physical design data across subsystem boundaries.

Mentor junior engineers and collaborate with cross-functional teams to resolve design, timing, and physical implementation challenges.

Present technical solutions and lead discussions with internal teams and customers regarding subsystem-level trade-offs and integration.

  • 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design.
  • Demonstrated expertise in STA tools and PNR tools applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows.
  • Deep understanding of SoC design flows and collaboration across frontend, physical design, and verification teams.
  • Experience with IP collateral generation and quality assurance preferred.
Requirements

Excellent communication skills, leadership abilities, and strong technical expertise in STA and PNR.

Familiarity with advanced technology nodes (7nm, or below) and high-speed interfaces/mixed-signal SoC subsystems.

What We Offer

A dynamic work environment, opportunities for professional growth, and recognition of individual achievements.

About the Role

This is a key role in our organization, requiring a skilled engineer with a passion for delivering exceptional results.

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