Senior ASIC Design Engineer

4 days ago


Hyderabad, Telangana, India Mulya Technologies Full time

**Job Overview**

Mulya Technologies, a well-funded US-based hardware product startup, is seeking a talented Senior ASIC Design Engineer with expertise in high-performance CXL/PCIe microarchitecture and design.

This role offers a great opportunity to help design cutting-edge compute and memory systems that push the boundaries on performance, energy efficiency, and scalability. As a full-time position based in Hyderabad, India, you will work with our team to develop innovative solutions for the future of computing.

**Job Responsibilities**
  • Architectural Exploration: Conduct thorough exploration of CXL and PCIe IP to build power, performance, and area-efficient memory expansion cards and SoCs.
  • Microarchitecture Development: Develop and document high-performance CXL/PCIe IP microarchitecture, ensuring it meets stringent requirements.
  • RTL Coding and Integration: Perform efficient RTL coding in Verilog or System Verilog, integrating CXL/PCIe IP modules into memory expansion cards and SoCs.
  • System and Firmware Collaboration: Work closely with systems and firmware teams to bring up CXL and PCIe on silicon platforms.
  • Verification and Performance: Collaborate with verification and performance teams to ensure the design is functionally correct and meets performance targets.
  • Emulation and FPGA Prototyping: Work with emulation and FPGA teams for design prototyping and functional/performance evaluation.

**Requirements**
  • Prior Experience: Hands-on work experience in high-performance CXL and PCIe IP or controller design.
  • Deep Expertise: In-depth knowledge as a microarchitect and RTL design engineer in developing high-performance digital IP.
  • Understanding of Microarchitecture Techniques: Strong understanding of high-performance and low-power microarchitecture techniques and logic design principles.
  • Coding Proficiency: Proficiency in Verilog or System Verilog coding, with the ability to identify PPA efficiency enhancements in RTL.
  • Front-end EDA Tools: Experience with front-end ASIC design EDA tools like simulators, waveform debuggers, IDEs, etc.
  • Educational Background: Master's, PhD, or bachelor's degree in a relevant subject area.

Estimated salary: ₹30-50 lakhs per annum (dependent on experience and qualifications). We offer a competitive compensation package, including benefits and opportunities for growth and development.



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