Senior ASIC Design Engineer
3 weeks ago
We are Jones RecruitZo, a leading recruitment agency in the field of technology and engineering. We are currently looking for a highly skilled Senior ASIC Design Engineer to join our team.
The successful candidate will be responsible for implementing logical and physical optimization for timing closure, as well as developing timing constraints and delivering synthesized netlists to the physical design team. They will also provide constraints support for PD STA and have hands-on experience with development of timing and design constraints.
A strong background in CMOS logic Design fundamentals is essential, as is knowledge and exposure to Digital System Design using HDL-Verilog. Competence in Custom Layout Design utilizing Cadence Virtuoso is also required. The ideal candidate will have familiarity with ASIC design flows across lower nodes, including 3nm, 7nm, and 14nm nodes, and be capable of simultaneously handling multiple blocks.
We offer a competitive salary of $120,000 - $150,000 per year, depending on experience, as well as a range of benefits including health insurance, retirement savings plan, and paid time off.
Requirements:
- BS/MS degree in Electrical Engineering or Computer Science
- 5+ years of experience in ASIC design and development
- Strong background in CMOS logic Design fundamentals
- Knowledge and exposure to Digital System Design using HDL-Verilog
- Competence in Custom Layout Design utilizing Cadence Virtuoso
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