Senior Verification Engineer for Mixed Signal ASIC

6 days ago


Hyderabad, Telangana, India Pplability INC Full time
About the Role
As a Senior Verification Engineer for Mixed Signal ASIC at Pplability INC, you will be responsible for leading the functional verification of our state-of-the-art mixed signal Sensor ASIC. This is an excellent opportunity to leverage your expertise in UVM methodologies and UVCs to drive innovation and quality.

Key Responsibilities
• Own the development of reusable code used over multiple product generations
• Partner with team members, designers, and architects to understand and verify the functionality within the context of the block, chip, and overall system
• Document and execute test plans consisting of directed and constrained-random tests
• Develop functional coverage and use feedback from code and functional coverage to enhance verification efforts
• Provide technical guidance and innovative ideas to improve quality, processes, and productivity

Requirements
• B.Tech/M.Tech in Electronics & Communication Engg.
• Experience - Minimum 5+ years with complex ASIC projects
• Strong background in System Verilog and UVM methodologies and UVCs
• Proficient in OO programming, computer architecture, and data structures
• Extensive experience with UVM test bench construction
• Experience with AMS design verification is a plus
• Knowledge of Python and Makefiles

What We Offer
The salary for this position is ₹12,00,000 per annum, which is commensurate with industry standards considering the location and requirements.

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