Physical Design Engineer
4 weeks ago
About the Role
Lattice Semiconductor is seeking a highly skilled Physical Design Engineer to join our team in Pune, India. As a key contributor to our FPGA design efforts, you will be responsible for driving physical design closure of key ASIC blocks and full chip, while bringing best-in-class methodologies to achieve best power, performance, and area.
Key Responsibilities
- Implement RTL to GDSII flow for complex ASIC design
- Expertise in one or more aspects of physical design including place & route, CTS, routing, floorplanning, powerplanning
- Experience in physical design signoff checks, including timing closure, EM/RV and physical verification (DRC, LVS)
- Collaborate with RTL, DFT, verification and full chip teams to ensure robust design implementation
Requirements
- BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent
- 5+ years of experience in driving physical design activities of ASIC blocks and full chip
- Experience working with industry standard physical design tools including Innovus, Genus, Tempus, voltus, calibre, conformal
About Lattice Semiconductor
Lattice Semiconductor is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.
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