Senior Physical Design Engineer
2 weeks ago
About the Role
Lattice Semiconductor is seeking a highly skilled Physical Design Engineer to join our team. As a member of our design team, you will be responsible for implementing RTL to GDSII flow for complex ASIC designs.
Responsibilities
- Implement RTL to GDSII flow for complex ASIC designs.
- Expert in one or more aspects of physical design including place & route, CTS, routing, floorplanning, powerplanning.
- Experience in physical design signoff checks, including timing closure, EM/RV and physical verification (DRC, LVS).
- Collaborate with RTL, DFT, verification and full chip teams to ensure robust design implementation.
- Serve as a key contributor to FPGA design efforts.
- Drive physical design closure of key ASIC blocks & full chip and bring best-in-class methodologies to achieve best power, performance, and area.
Requirements
- BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.
- 5+ years of experience in driving physical design activities of ASIC blocks and full chip.
- Experience on working with industry standard physical design tools including Innovus, Genus, Tempus, voltus, calibre, conformal etc.
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