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4 days ago
Drive innovative advancements in silicon architecture and design as a seasoned PhD professional. Collaborate with cross-functional teams to craft high-performance hardware/software interfaces for AI/ML applications, optimizing power, performance, and cost.
Responsibilities:
- Elevate the design and optimization of next-generation TPUs for complex AI/ML workloads.
- Develop and evaluate architectural and microarchitectural models to identify power/performance trade-offs for TPUs.
- Implement cutting-edge AI/ML techniques to optimize physical design convergence, timing, and floor planning for TPUs.
Requirements:
- Hold a PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field.
- Possess experience with accelerator architectures, data center workloads, and programming languages (C++, Python, Verilog).
- Post-PhD experience (2 years preferred) with performance modeling tools and memory hierarchy design.
- Exhibit strong knowledge in high-performance and low-power design techniques for hardware accelerators.
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