
Senior Microarchitecture Engineer for On-Chip Interconnects
1 week ago
Job Overview:
We are seeking an experienced Senior Microarchitecture Engineer to join our elite team of engineering professionals. As a key member of the Systems division, you will be responsible for the design and development of high-bandwidth, low-latency on-chip interconnects (NoC) and chip-to-chip interconnects.
Main Responsibilities:
- Design and architect different interconnect topologies driven by bandwidth, latency, and RAS requirements
- Develop features and present proposed architectures in high-level design discussions
- Collaborate with verification, DFT, physical design, firmware, and software teams to develop features
- Sign off pre-silicon designs that meet functional, area, and timing goals
- Participate in silicon bring-up and validation of hardware
Requirements:
- Master's degree in Computer Science or related field
- 8+ years of relevant experience
- Expertise in processor interconnect design delivery leadership
- Experience in different on-chip interconnect topologies
- Understanding of snoop and data network protocols
- Proficient in HDLs - VHDL/Verilog
- Experience in high-speed and power-efficient logic design
About This Role:
This is an exciting opportunity to work on cutting-edge technologies and contribute to the development of next-generation systems.
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