
Principal Design Engineer
2 days ago
We are seeking a highly skilled Senior DFT Engineer to join our team. As a senior member of the design team, you will be responsible for developing and implementing Digital Fault Tolerance (DFT) architecture for ASIC/SoC designs.
- Develop and implement DFT architecture for ASIC/SoC designs.
- Insert and verify scan chains, boundary scan (JTAG), MBIST, LBIST, and other test structures.
- Collaborate with RTL and physical design teams to ensure seamless integration of DFT features.
- Generate and validate test patterns using ATPG tools for stuck-at, transition, and path delay faults.
- Perform fault simulation and coverage analysis to optimize test quality.
- Support silicon bring-up and debug of test-related issues.
- Work with ATE teams to develop test programs and support production testing.
In this role, you will have the opportunity to work on challenging projects, collaborate with a talented team, and contribute to the development of cutting-edge technologies.
If you are a motivated and experienced DFT engineer looking for a new challenge, please submit your application.
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Principal Engineer
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Ahmedabad, Gujarat, India ACL Digital Full timeHiring of Principal EngineerExperience range: 6 to 8 yearsLocation : AhmedabadMust:Understanding of Ethernet Standards: IEEE 802.3 (10/100/1000BASE-T, 2.5G/5G/10GBASE-T, NBASE-T, Fiber Optics).Ethernet PHY ICs: Internal blocks (PCS, PMA, PMD), Auto-negotiation, Link Training, FEC, Loopbacks.Media Independent Interfaces (MIIs): MII, RMII, GMII, RGMII, SGMII,...
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Principal Engineer
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Ahmedabad, Gujarat, India ACL Digital Full timeHiring of Principal Engineer Experience range: 6 to 8 years Location : Ahmedabad Must: Understanding of Ethernet Standards: IEEE 802.3 (10/100/1000BASE-T, 2.5G/5G/10GBASE-T, NBASE-T, Fiber Optics). Ethernet PHY ICs: Internal blocks (PCS, PMA, PMD), Auto-negotiation, Link Training, FEC, Loopbacks. Media Independent Interfaces (MIIs): MII, RMII, GMII, RGMII,...
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