Chief DFT Architect

1 week ago

Coimbatore, Tamil Nadu, India beBeeDesign Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Design for Test (DFT) Engineer

We are seeking an experienced Design for Test (DFT) Engineer to join our team. As a key member of our engineering organization, you will be responsible for defining and implementing DFT architectures for complex System-on-Chip (SoC) designs.

Your primary focus will be on planning, executing, and delivering scan, ATPG, MBIST, and boundary scan insertion and validation. You will work closely with EDA vendors to evaluate, deploy, and optimize DFT tool flows.

In addition to your technical expertise, you will be expected to automate repetitive tasks using scripting to improve efficiency and reduce errors. You will also provide technical guidance and mentorship to junior engineers in the DFT team.

Required Skills and Qualifications:
  • Strong expertise in DFT architectures and methodologies, including but not limited to: Scan Insertion & Verification, ATPG (Automatic Test Pattern Generation), MBIST (Memory Built-In Self-Test), JTAG / Boundary Scan.
  • Hands-on experience with industry-standard DFT tools and methodologies from Cadence, Synopsys, and Mentor Graphics (Siemens EDA).
  • Proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.
  • Solid understanding of SoC design cycle, RTL to GDSII flow, and test requirements.
  • Experience collaborating with RTL designers, verification engineers, and physical design teams to ensure seamless DFT integration.
  • Strong problem-solving skills, ability to debug complex test issues, and deliver high-quality DFT solutions within tight schedules.
Benefits:
  • Opportunity to work on complex and challenging projects that will help shape the future of SoC design.
  • Collaborative and dynamic work environment with experienced professionals.
  • Chance to grow and develop your skills through continuous learning and professional development.
Others:
  • Preferred Skills (Nice to Have): Knowledge of low-power DFT techniques, experience with post-silicon bring-up and ATE patterns, familiarity with safety-critical standards (ISO 26262, DO-254, etc.).
  • Exposure to High-Speed IO testing (SERDES, DDR, etc.).

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