Senior Verification Engineer

1 month ago


Bengaluru, Karnataka, India Analog Devices Full time
Job Description

We are seeking a highly skilled Senior Verification Engineer to join our team at Analog Devices. As a key member of our digital verification team, you will be responsible for designing and implementing verification plans, test scenarios, and verification methodologies for RF/Bluetooth modules.

Key Responsibilities
  • Develop and implement verification plans, test scenarios, and verification methodologies for RF/Bluetooth modules.
  • Collaborate with digital and analog design teams to generate and review verification plans and closure of code and functional coverage.
  • Deploy industry-standard UVM-based verification approaches and develop self-checking test cases.
  • Work closely with team members from various disciplines to achieve first-pass silicon.
  • Support test and characterization teams in post-silicon validation.
  • Mentor junior engineers and contribute to the development of next-generation innovative design verification methodologies.
Requirements
  • B.Tech/M.Tech with 8+ years of industry experience in digital pre-silicon verification of RF/Bluetooth modules.
  • Good understanding of RF/Bluetooth digital and analog architectures and exposure to products that integrate a wide variety of RF/Bluetooth-related wireless modules.
  • Experience in verification plan development, verification environment development using UVM, and verification/debug of complex products involving RF/Bluetooth modules.
  • Experience in closing verification of blocks, subsystem-level verification using industry-standard metrics like code and functional coverage.
  • Power-aware verification with UPF, power analysis, and power optimization.
  • Gate-level simulation with timing-annotated.
  • Assertion and formal knowledge are an advantage.
  • Experience and debug with digital simulators such as Cadence Xcelium/Synopsys VCS.
  • Tracking of verification metrics and regression management, Metric-Driven Verification (MDV) framework using tools such as Cadence vManager.
  • System Verilog, C/C++, System C, TCL/Python/shell-scripting.
  • Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to a wider team spread across the globe.
Preferred Qualifications
  • Experience in formal verification and defining formal verification flows, connectivity, and functional verification using formal tools.
  • Experience in working with digital/analog design teams to generate and review verification plans and closure of code and functional coverage.
  • Experience in deploying industry-standard UVM-based verification approaches and developing self-checking test cases.

Job Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days



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