
Advanced Mixed Signal Chip Designer
4 days ago
We are seeking a highly skilled Senior ASIC STA Engineer to lead synthesis, static timing and DFT efforts for an advanced mixed signal chip.
This is a key position in our SOC digital design team, where you will provide integrated solutions and work closely with customers to define methodologies and design flows.
Our engineers work on cutting-edge technology nodes while tackling state-of-the-art designs in AI/ML, Datacenter, Automotive and 5G domains.
The successful candidate will require thorough knowledge of the ASIC design timing closure flow and methodology. At least 6+ years hands-on experience in ASIC timing constraints generation and timing closure is essential.
Main Responsibilities:
- Full chip and block level timing closure ownership throughout the project cycle
- Developing and maintaining methodology and flows related to timing verification and closure
- Analyzing timing reports and utilizing scripting techniques to develop insights and drive rapid timing closure
Our engineers are passionate about pushing the boundaries of innovation and delivering exceptional results. If you share our commitment to excellence and are eager to take on new challenges, we would love to hear from you.
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