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1 day ago
We are seeking an experienced Timing Closure Specialist to join our team.
- Key Responsibilities:
- Set up, execute, and close the GPU STA environment for multiple voltage domains.
- Drive pre-route timing checks and QoR cleanup to eliminate SDC issues and ensure a quality handoff for STA checks.
- Ensure timing correlation between PnR STA and timely feedbacks to PD team.
- Generate block-level HS sessions and use SoC top context for Block-SoC Interface timing closure.
- Generate timing ECO using Tweaker/PrimeClosure.
Requirements:
- 3+ years of experience in timing closure of high-frequency blocks like CPU/GPU (GHz range).
- Analyze timing reports and identify design and constraint-related issues.
- Work on blocks with multiple power and voltage domains.
- Familiarity with EDA tools Primetime, Tweaker/PrimeClosure, Innovus is a must.
- Strong understanding of DFT modes requirements for timing signoff.
- Good understanding of physical design flow and ECO implementation.
- Strong understanding of SDC constraints, OCV, AOCV, POCV analysis.
- Excellent TCL/scripting knowledge is mandatory.
Education:
- Bachelors or Masters degree in Electrical Engineering.
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