
Distinguished DFT Engineering Professional
1 week ago
Our organization is seeking a seasoned Digital Fault Tolerance (DFT) expert to lead our team in the development of advanced test methodologies and technologies.
- The ideal candidate will have extensive experience with IJTAG, P1500 protocols, and hands-on knowledge of industry-standard tools such as Cadence, Siemens Tessent, and Synopsys.
- A strong understanding of BSCAN, MBIST, SCAN, ATPG, and Simulation concepts is essential for this role.
- Responsibilities will include designing and implementing complex digital fault tolerance strategies, conducting simulations using industry-standard simulators like VCS, NCSim, or Xcelium, and collaborating with cross-functional teams to ensure seamless project execution.
- The successful candidate will have worked on various fault models including stuck-at, Transition Delay Faults (TDF), IDDQ, and possess expertise in scan test coverage improvement techniques.
- SOC level DFT experience is crucial, encompassing OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes, and post-silicon bring-up and/or production activities.
- Excellent communication and debugging skills are necessary for this position, as it involves leading and mentoring DFT engineers, coordinating with customer teams, and ensuring timely delivery of projects.
Experience: 5+ years
About Our Organization:
We provide end-to-end custom SOC design solutions, ranging from SOC Architecture to RTL design, Design verification, DFT, Physical Design & Analog design. We focus on delivering high-quality solutions tailored to our clients' needs.
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