DFT Engineer

3 weeks ago


Bengaluru, India Coders Brain Technology Private Limited Full time

Design-for-Test (DFT) EngineerWe are looking for a skilled and experienced Design-for-Test (DFT) Engineer to join our team in Bangalore. The ideal candidate will have hands-on expertise in various DFT methodologies including scan insertion, MBIST, JTAG, ATPG, and pattern validation at both block and full-chip Responsibilities : - Perform scan insertion, MBIST, and boundary scan (JTAG) implementation.- Develop and validate ATPG patterns at block and chip level using industry-standard tools.- Execute scan compression, test point insertion, and generate fault models including Stuck-at, Transition, Bridging, and Cell-Aware.- Conduct ATPG coverage analysis and provide actionable insights for optimization.- Perform DFT mode timing analysis and sign-off.- Debug gate-level simulations and ensure pattern correctness.- Collaborate with cross-functional teams across RTL design, synthesis, constraints, and timing closure.- Support post-silicon bring-up and debug (a Skills : - Strong understanding of DFT concepts : Scan insertion, ATPG, MBIST, boundary scan (JTAG), pattern validation.- Hands-on experience with Synopsys DFT tools : DFT MAX, TetraMAX, VCS.- Proficiency in ATPG coverage reporting and improvement strategies.- Familiarity with industry-standard fault models : Stuck-at, Transition, Bridging, Cell-Aware.- Experience with Spyglass DFT and related RTL linting tools.- Good command over Verilog and RTL-level simulation and debug.- Experience in gate-level pattern simulation and debug workflows.- Understanding of DFT architecture and design flows in ASIC development.- Exposure to post-silicon validation and debug (preferred but not Qualifications : - Bachelors or Masters degree in Electrical / Electronics / VLSI Engineering or equivalent.- Strong analytical and problem-solving skills.- Ability to work independently and in a team-oriented environment.- Excellent verbal and written communication skills. (ref:hirist.tech)


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