Senior ASIC Design Engineer

2 weeks ago

Morādābād, Uttar Pradesh, India beBeeDigitalFaultTolerance Full time ₹ 1,00,00,000 - ₹ 2,00,00,000
About This Role

The Digital Fault Tolerant (DFT) Engineer will be responsible for ensuring that DFT design rules and coverages are met in collaboration with ASIC design teams.

Key Responsibilities:

  • Collaborate with ASIC design teams to guarantee adherence to DFT design rules and coverages.
  • Generate high-quality manufacturing test patterns for stuck-at (SAF), transition fault (TDF) models through the application of on-chip test compression techniques.
  • Perform MBIST verification (including repair), test pattern generation using Mentor tool.
  • Execute ATPG (SAF, TDF) and MBIST verification utilizing unit delay and min/max timing corner simulations.
  • Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
  • Support post-silicon debug effort, issue resolution.
  • Develop Diagnostic Tool for ATPG, MBIST and bring-up on ATE.
  • Maintain and enhance scripts as necessary.

Requirements and Qualifications

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering required.
  • Minimum of 4 to 12 years' experience in ASIC/DFT - simulation and Silicon validation is necessary.
  • At least one Full chip DFT project experience is essential.
  • Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement is required.
  • In-depth understanding and hands-on experience in ATPG - coverage analysis is a must.
  • Expertise in Memory verification, repair and failure root-cause analysis is essential.
  • Experience with TestKompress, ETVerify and VCS tools is highly desirable.
  • Scripting languages like Perl and shell skills are an added advantage.
  • Strong communication and team working abilities are vital.
  • Adaptability to new tools and methodologies is a key requirement.
  • Able to prioritize multiple tasks and designs simultaneously.

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