Senior DFT Specialist

1 week ago

Surat, Gujarat, India beBeeDigitalFaultTolerance Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

Job Overview:

We are seeking a seasoned Digital Fault Tolerance (DFT) engineer to join our team.

The ideal candidate will have in-depth knowledge of DFT concepts, pattern simulation, and silicon debug, with a strong background in ASIC/DFT.

Key Responsibilities:
  • Collaborate with ASIC design teams to ensure adherence to DFT design rules and coverages.
  • Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques.
  • Perform MBIST verification, including repair, and test pattern generation through Mentor tools.
  • Conduct ATPG and MBIST verification using unit delay and min/max timing corner simulations.
  • Work closely with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
  • Support post-silicon debug efforts and issue resolution.
  • Develop and maintain scripts as necessary.
Required Skills and Qualifications:
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field.
  • Minimum 4-12 years' experience in ASIC/DFT, with a proven track record in simulation and silicon validation.
  • Expertise in DFT concepts, pattern simulation, and silicon debug.
  • Strong understanding of ATPG and MBIST methodologies.
  • Proficiency in scripting languages such as Perl, shell, etc.
  • Excellent communication and collaboration skills.
Preferred Experience:
  • Detailed knowledge of memory verification, repair, and failure root-cause analysis.
  • Experience with tools like TestKompress, MentorETVerify, VCS, ModelSim.
  • Ability to work in an international team environment.
  • Capacity to learn and adapt to new tools and methodologies.
  • Ability to multitask and prioritize multiple projects simultaneously.

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