
Timing Expert
3 days ago
Job Title:
Senior Timing Methodology EngineerJob Description:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience.
- Masters degree in Computer Science, Electrical/Electronics Engineering, or a related field with 1+ year of hardware engineering experience.
- OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with 4+ years of hardware engineering experience.
- Masters degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience.
Key Responsibilities:
- Lead the deployment of new features and methodologies related to STA and ECO domains.
- Scope of work includes STA flow/methodology development, continuous efficiency improvement, flow development/support for ECO convergence with tools in STA and ECO domains.
- Resolve timing convergence challenges at both block and top levels on cutting-edge technology for high-performance designs to ensure successful design tapeouts on time with high quality.
Requirements:
- Thorough knowledge of the ASIC design cycle and timing closure flow and methodology.
- Proficiency in timing constraints and timing closure with expertise in STA tools (Primetime, Tempus, Tweaker) and flow.
- Strong understanding of advanced STA concepts and challenges in advanced nodes.
- Proficiency in scripting languages (TCL, Perl, Python).
- Strong background in PNR and extraction domains.
- Leadership qualities to lead (technically) and manage the STA CAD team.
Qualification:
- BE/BTech + 4 years of experience, or ME/MTech + 3 years of experience.
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