
Semiconductor Solutions Designer
6 days ago
We are seeking a highly skilled Physical Design Engineer to take on the challenge of designing and optimizing complex semiconductor solutions.
The ideal candidate will have in-depth knowledge of ASIC physical design, including floor planning, placement, routing, and timing closure.
Key responsibilities will include top-level floor planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
A strong background in advanced low power techniques such as Voltage Islands, Power Gating and substrate-bias is essential for success in this role.
Additionally, the selected candidate will provide technical guidance and mentoring to junior engineers, interface with front-end ASIC teams to resolve issues, and work on Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
Timing closure on DDR2/DDR3/PCIE interfaces is also a key requirement.
Familiarity with Cadence or Synopsys or Magma physical Design Tools is required, along with expertise in scripting languages such as PERL, TCL.
A strong Physical Verification skill set and experience in Static Timing Analysis in Primetime or Primetime-SI are also essential.
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