Lead ASIC Physical Designer

2 days ago


Erode, Tamil Nadu, India beBeePhysical Full time ₹ 1,20,00,000 - ₹ 2,50,00,000

**Job Summary**

We are seeking an experienced Senior Physical Design Engineer with 4-12 years of experience to lead our team in the design and development of advanced low-power integrated circuits.

The successful candidate will be responsible for:

  • Top-level floor planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
  • Design of 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias.
  • Providing technical guidance, mentoring to physical design engineers.
  • Interface with front-end ASIC teams to resolve issues.
  • Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
  • Timing closure on DDR2/DDR3/PCIE interfaces.

**Key Requirements**

  • Excellent communication skills.
  • Strong background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
  • Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
  • Expertise in scripting languages such as PERL, TCL.
  • Strong Physical Verification skill set.
  • Static Timing Analysis in Primetime or Primetime-SI.


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