Senior Verification Engineer

1 month ago


Bengaluru, Karnataka, India Eteros Technologies Full time
Job Title:

Power Domain Implementation (Low-Power/IR-Drop/Reliability) Engineer

Job Summary:

We are seeking a highly skilled Senior Verification Engineer to join our team at Eteros Technologies. The successful candidate will work on design verification of state-of-the-art SOCs and/or IPs at cutting-edge FinFET technology nodes for various customers.

Key Responsibilities:
  • Design verification of complex IPs, blocks, sub-systems, and SOC-level designs
  • Guide peers and junior engineers working on design verification aspects
  • Work hands-on on critical blocks/tasks
  • Build and execute SOC verification flows, methodologies, and verification of SoCs
Requirements:
  • Understanding of all phases of the IC design process from specification to post-Si
  • Design verification of IP-level, SOC-level, and/or block-level/sub-system-level designs
  • Experience in high-speed, low-power, mixed-signal designs is a plus
  • Experience in developing verification plans, verification methodologies, and flows from scratch
  • Hands-on expertise with UMV (or similar) methodology, and Verilog/System Verilog (SV)
  • Experience in low-power verification using UPF/CPF power intent flows is a plus
  • Experience in constraint-random verification and/or transaction-based verification
  • Experience in one or more of the IPs like LPDDR-4&above, PCIE-Gen3&above, SATA, USB 3.0&above, Ethernet, DDR, NVMe, SDMM, MIPI etc.
  • Experience with on-chip protocols like AXI/AXI-Lite, AMBA/AHB/APB etc.
  • Experience with gate-level simulations - timing/no-timing, SDF annotation
  • Experience in developing one or more of - monitors, sequencers, drivers, scoreboards, checkers, coverage analysis/metrics, coverage closure, assertions, VIP components etc.
  • Strong scripting skills with C/C++/Perl/Python
  • Understanding of emulations platforms, S/W co-development, end-to-end verification
  • EDA Tools: Industry standard tools from Synopsys, Cadence, Mentor etc.
Qualifications:
  • BTech/MTech/PhD with 3-10 years' experience in ASIC/SOC/IP design verification
  • Proven track record with multiple successful ASIC/SOC design verification projects
  • Proven ability to independently deliver results in a very fast-moving start-up environment, be able to work hands-on as and when needed
  • Be able to work under limited supervision and take complete accountability
  • Excellent written and verbal communication skills
What's in it for you:
  • Work on leading-edge technologies
  • An opportunity for career development and growth
  • Competitive compensation & Exceptional benefits


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