
Chief Digital Fault Tolerance Architect
6 days ago
Job Overview
We are seeking a skilled Digital Fault Tolerance (DFT) Engineer to develop and implement DFT architecture with a focus on Built-In Self-Test (BIST) for advanced System-on-Chips (SoCs).
The ideal candidate will have hands-on experience in DFT with a strong focus on Automatic Test Pattern Generation (ATPG), SCAN, and BIST.
Responsibilities:
- Integrate BIST Intellectual Property (IPs), generate test insertion and verification infrastructure, and perform ATPG and BIST pattern generation and debug failures from silicon bring-up.
- Collaborate with RTL, Physical Design, and Verification teams throughout the design cycle.
- E nsure high coverage and test quality in scan and BIST.
Requirements:
To be successful in this role, you should have:
- Bachelor's or Master's degree in Electronics or related field.
- Minimum 7+ years of hands-on experience in DFT with a strong focus on ATPG, SCAN, and BIST.
- Proficient in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent.
- Solid understanding of scan insertion, ATPG, boundary scan, and JTAG.
- Experience with memory test algorithms, repair analysis, and pattern generation.
- Familiarity with scripting languages (TCL, Perl, Python) for automation.
- Strong analytical and problem-solving skills with the ability to work independently.
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