Digital Fault Tolerance Expert

2 days ago


Dindigul, Tamil Nadu, India beBeeDft Full time ₹ 15,00,000 - ₹ 20,00,000

Job Title : DFT Engineer/Senior Engineer/Lead Engineer/DFT Architect

Experience: 4-12 years

Location: Bangalore, Hyderabad, Kochi, Pune

Key Responsibilities:

  • Interface with ASIC design teams to ensure DFT design rules and coverages are met.
  • Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.
  • MBIST verification (including repair), test pattern generation through Mentor tool.
  • ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
  • Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
  • Responsible for supporting post-silicon debug effort, issue resolution.
  • Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.
  • Developing, enhancing and maintaining scripts as necessary.


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