Chief Design For Test Architect

1 week ago

Tirupati, Andhra Pradesh, India beBeeDesignForTest Full time ₹ 8,00,000 - ₹ 15,00,000
Job Overview

The role of a Design for Test (DFT) Engineer is pivotal in ensuring the quality and reliability of complex Systems-on-Chip (SoCs). As a DFT Engineer, you will be responsible for driving the definition and implementation of DFT architectures for SoCs.

Key Responsibilities:

  • Develop and execute scan, ATPG, MBIST, and boundary scan insertion and validation strategies.
  • Collaborate with EDA vendors to evaluate, deploy, and optimize DFT tool flows.
  • Automate repetitive tasks using scripting to improve efficiency and reduce errors.
  • Support test vector generation and validation for Automated Test Equipment (ATE).
  • Provide technical guidance and mentorship to junior engineers in the DFT team.

Required Technical Expertise:

  • Deep understanding of DFT architectures and methodologies, including but not limited to: Scan Insertion & Verification, ATPG (Automatic Test Pattern Generation), MBIST (Memory Built-In Self-Test), JTAG / Boundary Scan.
  • Hands-on experience with industry-standard DFT tools and methodologies from Cadence, Synopsys, and Mentor Graphics (Siemens EDA).
  • Proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.
  • Solid understanding of SoC design cycle, RTL to GDSII flow, and test requirements.

PREFERRED SKILLS:

  • Knowledge of low-power DFT techniques (power-aware ATPG, retention flops, etc.).
  • Experience with post-silicon bring-up and ATE patterns.
  • Familiarity with safety-critical standards (ISO 26262, DO-254, etc.).
  • Exposure to High-Speed IO testing (SERDES, DDR, etc.).

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