High-Speed Interface IP Design Professional

2 days ago


Hyderabad, Telangana, India beBeeEngineer Full time ₹ 2,31,00,000 - ₹ 2,63,00,000
High-Speed Interface IP Design Engineer

We are seeking an experienced High-Speed Interface IP Design Engineer to join our team. The ideal candidate will have a strong background in complex digital and mixed-signal design, with a particular emphasis on interfaces such as UCIe, Die-to-Die (D2 D), and various memory PHYs (DDR/LPDDR). Expertise in advanced clocking architectures including PLLs and DLLs is also essential.

Key Responsibilities:
  • Design & Development: Architect, design, and implement high-speed interface IPs, including UCIe, D2 D, DDR, and LPDDR PHYs.
  • Clocking Design: Develop and optimize PLL (Phase-Locked Loop) and DLL (Delay-Locked Loop) circuits for high-speed clock generation and synchronization, ensuring low jitter and high accuracy.
  • IP Development Lifecycle: Participate in the complete IP design flow, including architectural definition, specification development, RTL coding, synthesis, static timing analysis (STA), and collaborating on physical design activities (GDSII).
  • Verification & Validation: Work closely with verification teams to define test plans, debug complex design issues, and lead pre-silicon and post-silicon validation efforts.
Required Qualifications:
  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
  • 15-25 years of experience in digital, mixed-signal, or analog IP design within the semiconductor industry.
  • Proven experience with high-speed interface designs such as UCIe, D2 D, DDR PHY, or LPDDR PHY.
  • Demonstrated experience in the design and optimization of PLLs and/or DLLs, including various types of frequency synthesizers and clock generation circuits.
  • Familiarity with the entire IP development flow from architectural concept to silicon validation.
  • Strong understanding of signal integrity, power integrity, and layout considerations for high-speed designs.


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