Principal Architect for High-Performance Computing Solutions

3 days ago

Hyderabad, Telangana, India beBeePrincipal Full time ₹ 36,00,000 - ₹ 42,00,000
Job Title: Principal IP/RTL Design Engineer

The role of a Principal IP/RTL Design Engineer is pivotal in the development of innovative IP blocks for TPU cores. This engineer will be responsible for designing and developing systolic arrays, vector units, and memory subsystems that focus on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration.

  • Design and develop IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems.
  • Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization.
  • Implement high-speed interconnects (e.g., AXI, NoC) for TPU / GPU data pipelines.
  • Optimize designs for high throughput, low latency, and power efficiency in AI workloads.
  • Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces.
  • Support synthesis, timing closure, and FPGA prototyping and Design Verification team.
  • Document microarchitecture and design specifications.

Required Skills and Qualifications:

  • Education: BS/MS in Electrical/Computer Engineering.
  • Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU / TPU-like architectures.
  • Skills:
  • Proficient in Verilog/SystemVerilog RTL design.
  • Knowledge of GPU/TPU architectures, systolic arrays, or matrix multiplication units.
  • Experience with AXI, NoC, or similar interconnect protocols.
  • Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces.
  • Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler).
  • Strong problem-solving and teamwork skills.

Key Benefits Include:

  • Opportunity to work on cutting-edge projects in AI acceleration.
  • Collaborative environment with experienced engineers.
  • Professional growth and development opportunities.

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