Principal Designer for High-Performance Systems

1 day ago

Hyderabad, Telangana, India beBeeNeoverse Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Job Opportunity

We are seeking a skilled IP/RTL Design Engineer to develop high-performance designs for ARM Neoverse-based SoCs, focusing on CMN fabric.

This role requires the ability to design and implement Verilog/System Verilog RTL for low-latency designs, integrate CMN topologies using Arm Socrates, and optimize designs for bandwidth, latency, and power in AI/HPC workloads.

The ideal candidate will have 10+ years of experience in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics, and expertise in Verilog/System Verilog RTL design, deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects.

Key Responsibilities:

  • Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect.
  • Develop Verilog/System Verilog RTL for high-performance, low-latency designs.
  • Configure CMN topologies using Arm Socrates for optimized performance and scalability.
  • Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects.
  • Optimize designs for bandwidth, latency, and power in AI/HPC workloads.

Required Qualifications:

  • Education: BS/MS/PhD in Electronics/Computer Engineering.
  • Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3).
  • Skills: Expertise in Verilog/System Verilog RTL design, deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects, experience with Arm Socrates for CMN configuration, proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols, familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler), experience with AI/HPC or datacenter SoC design, knowledge of DDR5, HBM3, or chiplet-based architectures, familiarity with UALink or Ultra Ethernet.

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