Timing Engineer: High Frequency Blocks

As a senior engineer responsible for setting up and executing multi-voltage domain STA environment, you will drive pre-route timing checks and QoR cleanup to eliminate SDC issues. This role requires strong understanding of physical design flow, ECO implementation, and DFT modes requirements.Key Responsibilities:Setup and execute multi-voltage domain STA...

Timing Closure SpecialistWe are seeking a skilled Timing Closure Specialist to join our team. As a key member of our organization, you will be responsible for driving the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks.Your primary focus will be on ensuring timing correlation between PnR STA and...

Lead Physical Design EngineerWe are looking for a skilled professional to lead our physical design team.The ideal candidate will have extensive experience in high-frequency SoC designs, specifically in DDR and advanced node technologies.Main Responsibilities:Full flow ownership from RTL to GDSIIFloorplanning, power planning, placement, CTS, routing using...

Timing Closure SpecialistWe are seeking a skilled Timing Closure Specialist to join our team. In this role, you will play a crucial part in ensuring the timely completion of high-frequency designs while minimizing congestion and area-sensitive issues.Develop and refine timing closure knowledge for high-frequency designs, collaborating closely with Front-end...

Physical Design Engineering LeadWe are seeking a seasoned Physical Design Lead to spearhead high-frequency SoC designs, focusing on DDR and advanced node technologies. This expert will be responsible for guiding the RTL to GDSII implementation flow from start to finish.Key Responsibilities:Owning the complete design flow from RTL to GDSIIFloorplanning, power...

LTTS is looking for STA engineers with 5+ Years of experience, Detailed JD is mentioned below ::• Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs.• Can work closely with FE team for constraints development and constraints cleanup.• Work with partitions/block owner to give timing ECO for...

Job Title: STA EngineerKey Responsibilities:Responsible for setting up, executing, and closing timing for GPU in a multi-voltage domain STA environment.Drive pre-route timing checks and QoR cleanup to eliminate SDC issues and ensure quality handoffs for STA checks.Ensure timing correlation between PnR & STA and provide timely feedbacks to the PD...

Timing Closure SpecialistWe are seeking an experienced Timing Closure Specialist to join our team.Key Responsibilities:Set up, execute, and close the GPU STA environment for multiple voltage domains.Drive pre-route timing checks and QoR cleanup to eliminate SDC issues and ensure a quality handoff for STA checks.Ensure timing correlation between PnR STA and...

Static Timing Analysis Job OpportunityWe are looking for skilled STA engineers to join our team. As a STA engineer, you will play a crucial role in ensuring the timely and efficient completion of projects.The ideal candidate should have a minimum of 5+ years of experience in STA engineering. They should possess excellent knowledge of timing closure,...

Job Title: Signal Integrity Timing Closure SpecialistWe are seeking a highly skilled Signal Integrity Timing Closure Specialist to join our team.Key Responsibilities:Lead the setup, execution, and timing closure of complex multi-voltage domain environments for high-frequency blocks like GPU.Drive pre-route timing checks and quality-of-result (QoR) clean-up...