Senior DFT Architect

13 hours ago

Agra, Uttar Pradesh, India beBeeDft Full time ₹ 1,80,00,000 - ₹ 2,50,00,000

Job Title: Lead DFT Engineer

We are seeking a seasoned engineer to spearhead DFT architecture, planning, and implementation across intricate SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.

Key Responsibilities:
  • Develop and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  • Promote the implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, IJTAG, and manage end-to-end DFT flow.
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
  • Generate patterns, simulate faults, and debug test coverage gaps.
  • Oversight DFT signoff, timing closure, and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor and guide junior DFT engineers; conduct design reviews and training sessions.

Required Skills and Experience:

  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
  • Strong leadership, team collaboration, and communication skills.

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