Silicon Design Expert

3 days ago

Bengaluru, Karnataka, India beBeePhysical Full time ₹ 15,00,000 - ₹ 20,00,000

Job Summary

We are seeking an experienced Physical Design Engineer to join our team.

  • The ideal candidate will have a strong background in physical design, with expertise in timing analysis, synthesis and place & route.
  • Able to drive schedule and manage cost while delivering high-quality designs.

About the Role

This is a key position that requires collaboration among top-thinkers and engineers alike, ready to mentor and guide and help to elevate the knowledge and skills of the team around you.

Key Responsibilities:

  • RTL to GDS2 flow
  • Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR
  • Working on full chip timing analysis setup and signoff of multi-corner multi-voltage designs.; Hierarchical timing analysis and convergence at block, section and full chip level.
  • Engaging closely with Design teams to understand the design, constraints and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations.
  • Handling different PNR tools - Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Identify and implement opportunities for improving PPA

Preferred Experience:

  • 16+ years of professional experience in physical design, full chip timing and preferably with high performance designs.
  • Experience in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must.
  • Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
  • Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
  • Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
  • Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
  • Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl.
  • Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
  • Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm
  • Excellent physical design and timing background.
  • Good understanding of computer organization/architecture is preferred.
  • Strong analytical/problem solving skills and pronounced attention to details.

About Us

We offer a collaborative environment where you can grow your career and contribute to cutting-edge technology solutions.

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