Senior RTL Design Engineer

6 days ago


Alleppey, Kerala, India beBeeDesign Full time ₹ 1,50,00,000 - ₹ 2,00,00,000

Our company seeks a seasoned GDSII design engineer with expertise in RTL synthesis and timing analysis to drive innovation in Bangalore.

Key Responsibilities:
  • Develop and maintain comprehensive Design Compiler constraint files for optimal performance.
  • Perform thorough Pre-Timing Synthesis on complex RTL designs.
  • Execute rigorous Pre-Static Timing Analysis (Pre-STA) and support Physical Design activities.
  • Collaborate closely with cross-functional teams to achieve seamless design closure and deliver high-quality outcomes.

The successful candidate will possess a strong background in synthesis, static timing analysis, and physical design processes, with exceptional problem-solving skills to debug and resolve complex design and timing issues.

Essential Skills & Experience:
  • 6+ years of experience in RTL to GDSII design flow with proven success.
  • Hands-on expertise in crafting efficient DC constraint files.
  • Strong technical expertise in synthesis, STA, and physical design processes.

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